[Devel] [PATCH RHEL7 COMMIT] ms/KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

[Konstantin Khorenko]

The commit is pushed to "branch-rh7-3.10.0-862.9.1.vz7.63.x-ovz" and will appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-862.9.1.vz7.63.2
------>
commit 1cf4926337b9d21694bfb422f11fadf6b012c219
Author: Wanpeng Li <wanpeng.li at hotmail.com>
Date:   Wed Jul 25 18:47:08 2018 +0300

    ms/KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode
    
    If we take TSC-deadline mode timer out of the picture, the Intel SDM
    does not say that the timer is disable when the timer mode is change,
    either from one-shot to periodic or vice versa.
    
    After this patch, the timer is no longer disarmed on change of mode, so
    the counter (TMCCT) keeps counting down.
    
    So what does a write to LVTT changes ? On baremetal, the change of mode
    is probably taken into account only when the counter reach 0. When this
    happen, LVTT is use to figure out if the counter should restard counting
    down from TMICT (so periodic mode) or stop counting (if one-shot mode).
    
    This patch is based on observation of the behavior of the APIC timer on
    baremetal as well as check that they does not go against the description
    written in the Intel SDM.
    
    Cc: Paolo Bonzini <pbonzini at redhat.com>
    Cc: Radim Krčmář <rkrcmar at redhat.com>
    Signed-off-by: Wanpeng Li <wanpeng.li at hotmail.com>
    [Fixed rate limiting of periodic timer.]
    Signed-off-by: Radim Krčmář <rkrcmar at redhat.com>
    (cherry picked from commit dedf9c5e216902c6d34b5a0d0c40f4acbb3706d8)
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov at virtuozzo.com>
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov at virtuozzo.com>
    
    =====================
    Patchset description:
    
    Fix guest context switch performance degradation.
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Following patches were adopted from mainline kernel to fix guest Windows
    context switch performance degradation.
    
    VMX preemption timer support was added in kernel-3.10.0-862.3.2.el7. In this
    case, timer incorrectly triggers despite of its disabling and causes extra
    VMexit on every context switch. These patches add correct handling of disabled
    timer.
    
    Radim Krčmář (3):
      KVM: x86: handle 0 write to TSC_DEADLINE MSR
      KVM: x86: really disarm lapic timer when clearing TMICT
      KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch
    
    Wanpeng Li (3):
      KVM: LAPIC: Fix lapic timer mode transition
      KVM: LAPIC: Introduce limit_periodic_timer_frequency
      KVM: LAPIC: Keep timer running when switching between one-shot and
        periodic mode
---
 arch/x86/kvm/lapic.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 04c6fd357d6f..f16f16413992 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1356,7 +1356,7 @@ static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
 	 * interval, since the hrtimers are not throttled by the host
 	 * scheduler.
 	 */
-	if (apic_lvtt_period(apic)) {
+	if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
 		s64 min_period = min_timer_period_us * 1000LL;
 
 		if (apic->lapic_timer.period < min_period) {
@@ -1377,10 +1377,12 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
 
 	if (apic->lapic_timer.timer_mode != timer_mode) {
 		if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
-				APIC_LVT_TIMER_TSCDEADLINE))
+				APIC_LVT_TIMER_TSCDEADLINE)) {
 			kvm_lapic_set_reg(apic, APIC_TMICT, 0);
+			hrtimer_cancel(&apic->lapic_timer.timer);
+		}
 		apic->lapic_timer.timer_mode = timer_mode;
-		hrtimer_cancel(&apic->lapic_timer.timer);
+		limit_periodic_timer_frequency(apic);
 	}
 }