[Devel] [PATCH RHEL7 COMMIT] ms/x86/cpu: Keep model defines sorted by model number

[Konstantin Khorenko]

The commit is pushed to "branch-rh7-3.10.0-957.27.2.vz7.107.x-ovz" and will appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-957.27.2.vz7.107.13
------>
commit 213534ea31e80ba89fc608fe6b274eddf6e28e45
Author: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Date:   Thu Oct 3 18:38:08 2019 +0300

    ms/x86/cpu: Keep model defines sorted by model number
    
    For better maintenance keep it sorted by numeric model ID. Add new lines to
    seperate model groups.
    
    Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
    Cc: Dave Hansen <dave.hansen at linux.intel.com>
    Link: http://lkml.kernel.org/r/20170316155045.50389-1-andriy.shevchenko@linux.intel.com
    Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
    
    (cherry picked from commit c238f2343441e3995d2d4e993de42b072d005f4a)
    Signed-off-by: Jan Dakinevich <jan.dakinevich at virtuozzo.com>
    
    ==================================
    Patchset description:
    
    Rework the code for gathering LBR information.
    
     * Patches 1-5 pull newer definitions of Intel CPU models from upstream.
    
     * Patches 6-8 makes an attempt to rework existing implementation of LBR
       handling to make its further maintanance easier.
    
     * Also, patch 6 adds certain new cases from upstream to __intel_pmu_lbr_fill.
       However several models codes provided in intel-family.h remain unhandled.
       I can't find any information about these models:
    
       INTEL_FAM6_NEHALEM_G 0x1F
       INTEL_FAM6_CANNONLAKE_MOBILE 0x66
       INTEL_FAM6_ICELAKE_X 0x6A
       INTEL_FAM6_ICELAKE_XEON_D 0x6C
       INTEL_FAM6_ICELAKE_DESKTOP 0x7D
    
    Andy Shevchenko (1):
      x86/cpu: Keep model defines sorted by model number
    
    Jan Dakinevich (3):
      Revert "ms/perf/x86/intel: make reusable LBR initialization code"
      ms/perf/x86/intel: make reusable LBR initialization code, part 1/2
      ms/perf/x86/intel: make reusable LBR initialization code, part 2/2
    
    Kan Liang (2):
      x86/cpu: Add Atom Tremont (Jacobsville)
      x86/CPU: Add more Icelake model numbers
    
    Peter Zijlstra (1):
      x86/cpu: Sanitize FAM6_ATOM naming
    
    Rajneesh Bhardwaj (1):
      x86/CPU: Add Icelake model number
---
 arch/x86/include/asm/intel-family.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 8b72406d6e62..0a9784998efd 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -16,6 +16,7 @@
  */
 
 #define INTEL_FAM6_CORE_YONAH		0x0E
+
 #define INTEL_FAM6_CORE2_MEROM		0x0F
 #define INTEL_FAM6_CORE2_MEROM_L	0x16
 #define INTEL_FAM6_CORE2_PENRYN		0x17
@@ -25,6 +26,7 @@
 #define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
 #define INTEL_FAM6_NEHALEM_EP		0x1A
 #define INTEL_FAM6_NEHALEM_EX		0x2E
+
 #define INTEL_FAM6_WESTMERE		0x25
 #define INTEL_FAM6_WESTMERE_EP		0x2C
 #define INTEL_FAM6_WESTMERE_EX		0x2F
@@ -40,9 +42,9 @@
 #define INTEL_FAM6_HASWELL_GT3E		0x46
 
 #define INTEL_FAM6_BROADWELL_CORE	0x3D
-#define INTEL_FAM6_BROADWELL_XEON_D	0x56
 #define INTEL_FAM6_BROADWELL_GT3E	0x47
 #define INTEL_FAM6_BROADWELL_X		0x4F
+#define INTEL_FAM6_BROADWELL_XEON_D	0x56
 
 #define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
 #define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
@@ -65,8 +67,8 @@
 #define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Tangier */
 #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Annidale */
 #define INTEL_FAM6_ATOM_GOLDMONT	0x5C
-#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A
 #define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Goldmont Microserver */
+#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A
 
 /* Xeon Phi */