[CRIU] ARMv5 implementation
Maikel Coenen
maikel.coenen at nedap.com
Wed Mar 6 12:47:40 MSK 2019
Hi All,
Currently I am porting CRIU to ARMv5. I have already added/changed some code in atomic.h, bitops.S, compel/src/main.c and the Makefile. It is now compiling successfully but I get an error when restoring a simple bash application. (https://criu.org/Simple_loop)
The error reported is:
(834.884950 Error (criu/cr-restore.c:1433): 359 killed by signal 9: Killed
(834.886002 Error (criu/cr-restore.c:2309): Restoring FAILED.
When debugging with GDB, the following results are shown:
Thread 2.1 "criu" received signal SIGILL, Illegal instruction.
[Switching to Thread 0xb6ff8010 (LWP 359)]
0x0010ec88 in opts ()
And disassembling this address shows:
Dump of assembler code for function opts:
0x0010ec04 <+0>: 02 00 00 00 andeq r0, r0, r2
0x0010ec08 <+4>: 00 00 00 00 andeq r0, r0, r0
0x0010ec0c <+8>: 00 00 00 00 andeq r0, r0, r0
0x0010ec10 <+12>: 00 00 00 00 andeq r0, r0, r0
0x0010ec14 <+16>: 00 00 00 00 andeq r0, r0, r0
0x0010ec18 <+20>: 00 00 00 00 andeq r0, r0, r0
0x0010ec1c <+24>: 01 00 00 00 andeq r0, r0, r1
0x0010ec20 <+28>: 00 00 00 00 andeq r0, r0, r0
0x0010ec24 <+32>: 00 00 00 00 andeq r0, r0, r0
0x0010ec28 <+36>: 00 00 00 00 andeq r0, r0, r0
0x0010ec2c <+40>: 00 00 00 00 andeq r0, r0, r0
0x0010ec30 <+44>: 00 00 00 00 andeq r0, r0, r0
0x0010ec34 <+48>: 00 00 00 00 andeq r0, r0, r0
0x0010ec38 <+52>: 00 00 00 00 andeq r0, r0, r0
0x0010ec3c <+56>: 00 00 00 00 andeq r0, r0, r0
0x0010ec40 <+60>: 00 00 00 00 andeq r0, r0, r0
0x0010ec44 <+64>: 00 00 00 00 andeq r0, r0, r0
0x0010ec48 <+68>: 10 e5 11 00 andseq lr, r1, r0, lsl r5
0x0010ec4c <+72>: 00 00 00 00 andeq r0, r0, r0
0x0010ec50 <+76>: 00 00 00 00 andeq r0, r0, r0
0x0010ec54 <+80>: 00 00 00 00 andeq r0, r0, r0
0x0010ec58 <+84>: 58 ec 10 00 andseq lr, r0, r8, asr r12
0x0010ec5c <+88>: 58 ec 10 00 andseq lr, r0, r8, asr r12
0x0010ec60 <+92>: 60 ec 10 00 andseq lr, r0, r0, ror #24
0x0010ec64 <+96>: 60 ec 10 00 andseq lr, r0, r0, ror #24
0x0010ec68 <+100>: 68 ec 10 00 andseq lr, r0, r8, ror #24
0x0010ec6c <+104>: 68 ec 10 00 andseq lr, r0, r8, ror #24
0x0010ec70 <+108>: 70 ec 10 00 andseq lr, r0, r0, ror r12
0x0010ec74 <+112>: 70 ec 10 00 andseq lr, r0, r0, ror r12
0x0010ec78 <+116>: 00 00 00 00 andeq r0, r0, r0
0x0010ec7c <+120>: 00 00 00 00 andeq r0, r0, r0
0x0010ec80 <+124>: 00 00 00 00 andeq r0, r0, r0
0x0010ec84 <+128>: 00 00 00 00 andeq r0, r0, r0
=> 0x0010ec88 <+132>: ff ff ff ff ; <UNDEFINED> instruction: 0xffffffff
0x0010ec8c <+136>: 00 00 00 00 andeq r0, r0, r0
0x0010ec90 <+140>: 00 00 00 00 andeq r0, r0, r0
0x0010ec94 <+144>: 00 00 00 00 andeq r0, r0, r0
0x0010ec98 <+148>: 01 00 00 00 andeq r0, r0, r1
0x0010ec9c <+152>: 00 00 00 00 andeq r0, r0, r0
0x0010eca0 <+156>: 00 00 00 00 andeq r0, r0, r0
0x0010eca4 <+160>: 04 00 00 00 andeq r0, r0, r4
0x0010eca8 <+164>: 00 00 00 00 andeq r0, r0, r0
0x0010ecac <+168>: 00 00 00 00 andeq r0, r0, r0
0x0010ecb0 <+172>: 00 00 00 00 andeq r0, r0, r0
0x0010ecb4 <+176>: b4 ec 10 00 ; <UNDEFINED> instruction: 0x0010ecb4
0x0010ecb8 <+180>: b4 ec 10 00 ; <UNDEFINED> instruction: 0x0010ecb4
0x0010ecbc <+184>: 00 00 00 00 andeq r0, r0, r0
0x0010ecc0 <+188>: 00 00 00 00 andeq r0, r0, r0
0x0010ecc4 <+192>: 00 00 00 00 andeq r0, r0, r0
0x0010ecc8 <+196>: 00 00 00 00 andeq r0, r0, r0
0x0010eccc <+200>: 00 00 10 00 andseq r0, r0, r0
0x0010ecd0 <+204>: d0 ec 10 00 ; <UNDEFINED> instruction: 0x0010ecd0
0x0010ecd4 <+208>: d0 ec 10 00 ; <UNDEFINED> instruction: 0x0010ecd0
0x0010ecd8 <+212>: 00 00 00 00 andeq r0, r0, r0
0x0010ecdc <+216>: 00 00 00 00 andeq r0, r0, r0
0x0010ece0 <+220>: 0a 00 00 00 andeq r0, r0, r10
0x0010ece4 <+224>: 00 00 00 00 andeq r0, r0, r0
0x0010ece8 <+228>: 00 00 00 00 andeq r0, r0, r0
0x0010ecec <+232>: 00 00 00 00 andeq r0, r0, r0
0x0010ecf0 <+236>: cc 06 0d 00 andeq r0, sp, r12, asr #13
0x0010ecf4 <+240>: 00 00 00 00 andeq r0, r0, r0
0x0010ecf8 <+244>: 00 00 00 00 andeq r0, r0, r0
0x0010ecfc <+248>: 00 00 00 00 andeq r0, r0, r0
0x0010ed00 <+252>: ff ff ff ff ; <UNDEFINED> instruction: 0xffffffff
0x0010ed04 <+256>: 00 00 00 00 andeq r0, r0, r0
End of assembler dump.
Obviously something is not going quite right but at this point I am stuck how to go further. Probably some instruction is used which is not present in the ARMv5 instruction set but I don’t know where to find this instruction and which file I have to change. Does anyone know where/how to look at this error, so I can continue? Any insight is appreciated.
Thanks,
Maikel
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