[CRIU] [PATCH 34/38] compel: Move atomics and related into
Cyrill Gorcunov
gorcunov at openvz.org
Tue Oct 11 09:04:24 PDT 2016
All this (including cpuinfo) should evetually sit inside compel.
Signed-off-by: Cyrill Gorcunov <gorcunov at openvz.org>
---
.../aarch64/src/lib/include/compel}/asm/atomic.h | 0
.../arch/aarch64/src/lib/include/compel}/asm/cpu.h | 0
.../src/lib/include/compel}/asm/processor-flags.h | 0
.../arch/arm/src/lib/include/compel}/asm/atomic.h | 2 +-
.../arch/arm/src/lib/include/compel}/asm/cpu.h | 0
.../src/lib/include/compel}/asm/processor-flags.h | 0
.../arm/src/lib/include/compel}/asm/processor.h | 0
.../ppc64/src/lib/include/compel}/asm/atomic.h | 2 +-
.../ppc64/src/lib/include/compel}/asm/cmpxchg.h | 0
.../arch/ppc64/src/lib/include/compel}/asm/cpu.h | 0
.../src/lib/include/compel}/asm/processor-flags.h | 0
.../arch/x86/src/lib/include/compel}/asm/atomic.h | 2 +-
.../arch/x86/src/lib/include/compel}/asm/cmpxchg.h | 10 +-
compel/arch/x86/src/lib/include/compel/asm/cpu.h | 177 +++++++++++++++++++++
.../src/lib/include/compel}/asm/processor-flags.h | 0
criu/arch/aarch64/crtools.c | 2 +-
criu/arch/arm/crtools.c | 2 +-
criu/arch/x86/crtools.c | 2 +-
criu/arch/x86/include/asm/cpu.h | 177 +--------------------
criu/cr-restore.c | 2 +-
criu/files-reg.c | 2 +-
criu/include/cpu.h | 2 +-
criu/include/lock.h | 2 +-
criu/parasite-syscall.c | 2 +-
criu/stats.c | 2 +-
25 files changed, 195 insertions(+), 193 deletions(-)
rename {criu/arch/aarch64/include => compel/arch/aarch64/src/lib/include/compel}/asm/atomic.h (100%)
rename {criu/arch/ppc64/include => compel/arch/aarch64/src/lib/include/compel}/asm/cpu.h (100%)
rename {criu/arch/ppc64/include => compel/arch/aarch64/src/lib/include/compel}/asm/processor-flags.h (100%)
rename {criu/arch/arm/include => compel/arch/arm/src/lib/include/compel}/asm/atomic.h (98%)
rename {criu/arch/arm/include => compel/arch/arm/src/lib/include/compel}/asm/cpu.h (100%)
rename {criu/arch/arm/include => compel/arch/arm/src/lib/include/compel}/asm/processor-flags.h (100%)
rename {criu/arch/arm/include => compel/arch/arm/src/lib/include/compel}/asm/processor.h (100%)
rename {criu/arch/ppc64/include => compel/arch/ppc64/src/lib/include/compel}/asm/atomic.h (98%)
rename {criu/arch/ppc64/include => compel/arch/ppc64/src/lib/include/compel}/asm/cmpxchg.h (100%)
rename {criu/arch/aarch64/include => compel/arch/ppc64/src/lib/include/compel}/asm/cpu.h (100%)
rename {criu/arch/aarch64/include => compel/arch/ppc64/src/lib/include/compel}/asm/processor-flags.h (100%)
rename {criu/arch/x86/include => compel/arch/x86/src/lib/include/compel}/asm/atomic.h (97%)
rename {criu/arch/x86/include => compel/arch/x86/src/lib/include/compel}/asm/cmpxchg.h (91%)
create mode 100644 compel/arch/x86/src/lib/include/compel/asm/cpu.h
rename {criu/arch/x86/include => compel/arch/x86/src/lib/include/compel}/asm/processor-flags.h (100%)
diff --git a/criu/arch/aarch64/include/asm/atomic.h b/compel/arch/aarch64/src/lib/include/compel/asm/atomic.h
similarity index 100%
rename from criu/arch/aarch64/include/asm/atomic.h
rename to compel/arch/aarch64/src/lib/include/compel/asm/atomic.h
diff --git a/criu/arch/ppc64/include/asm/cpu.h b/compel/arch/aarch64/src/lib/include/compel/asm/cpu.h
similarity index 100%
rename from criu/arch/ppc64/include/asm/cpu.h
rename to compel/arch/aarch64/src/lib/include/compel/asm/cpu.h
diff --git a/criu/arch/ppc64/include/asm/processor-flags.h b/compel/arch/aarch64/src/lib/include/compel/asm/processor-flags.h
similarity index 100%
rename from criu/arch/ppc64/include/asm/processor-flags.h
rename to compel/arch/aarch64/src/lib/include/compel/asm/processor-flags.h
diff --git a/criu/arch/arm/include/asm/atomic.h b/compel/arch/arm/src/lib/include/compel/asm/atomic.h
similarity index 98%
rename from criu/arch/arm/include/asm/atomic.h
rename to compel/arch/arm/src/lib/include/compel/asm/atomic.h
index cd0df377245c..92e1a3df096c 100644
--- a/criu/arch/arm/include/asm/atomic.h
+++ b/compel/arch/arm/src/lib/include/compel/asm/atomic.h
@@ -1,7 +1,7 @@
#ifndef __CR_ATOMIC_H__
#define __CR_ATOMIC_H__
-#include "asm/processor.h"
+#include "compel/asm/processor.h"
typedef struct {
int counter;
diff --git a/criu/arch/arm/include/asm/cpu.h b/compel/arch/arm/src/lib/include/compel/asm/cpu.h
similarity index 100%
rename from criu/arch/arm/include/asm/cpu.h
rename to compel/arch/arm/src/lib/include/compel/asm/cpu.h
diff --git a/criu/arch/arm/include/asm/processor-flags.h b/compel/arch/arm/src/lib/include/compel/asm/processor-flags.h
similarity index 100%
rename from criu/arch/arm/include/asm/processor-flags.h
rename to compel/arch/arm/src/lib/include/compel/asm/processor-flags.h
diff --git a/criu/arch/arm/include/asm/processor.h b/compel/arch/arm/src/lib/include/compel/asm/processor.h
similarity index 100%
rename from criu/arch/arm/include/asm/processor.h
rename to compel/arch/arm/src/lib/include/compel/asm/processor.h
diff --git a/criu/arch/ppc64/include/asm/atomic.h b/compel/arch/ppc64/src/lib/include/compel/asm/atomic.h
similarity index 98%
rename from criu/arch/ppc64/include/asm/atomic.h
rename to compel/arch/ppc64/src/lib/include/compel/asm/atomic.h
index 4fa33b1c7005..1e4d2e04a172 100644
--- a/criu/arch/ppc64/include/asm/atomic.h
+++ b/compel/arch/ppc64/src/lib/include/compel/asm/atomic.h
@@ -11,7 +11,7 @@ typedef struct {
int counter;
} atomic_t;
-#include "asm/cmpxchg.h"
+#include "compel/asm/cmpxchg.h"
#define PPC_ATOMIC_ENTRY_BARRIER "lwsync \n"
#define PPC_ATOMIC_EXIT_BARRIER "sync \n"
diff --git a/criu/arch/ppc64/include/asm/cmpxchg.h b/compel/arch/ppc64/src/lib/include/compel/asm/cmpxchg.h
similarity index 100%
rename from criu/arch/ppc64/include/asm/cmpxchg.h
rename to compel/arch/ppc64/src/lib/include/compel/asm/cmpxchg.h
diff --git a/criu/arch/aarch64/include/asm/cpu.h b/compel/arch/ppc64/src/lib/include/compel/asm/cpu.h
similarity index 100%
rename from criu/arch/aarch64/include/asm/cpu.h
rename to compel/arch/ppc64/src/lib/include/compel/asm/cpu.h
diff --git a/criu/arch/aarch64/include/asm/processor-flags.h b/compel/arch/ppc64/src/lib/include/compel/asm/processor-flags.h
similarity index 100%
rename from criu/arch/aarch64/include/asm/processor-flags.h
rename to compel/arch/ppc64/src/lib/include/compel/asm/processor-flags.h
diff --git a/criu/arch/x86/include/asm/atomic.h b/compel/arch/x86/src/lib/include/compel/asm/atomic.h
similarity index 97%
rename from criu/arch/x86/include/asm/atomic.h
rename to compel/arch/x86/src/lib/include/compel/asm/atomic.h
index d447b65cb4c6..6d26b3911627 100644
--- a/criu/arch/x86/include/asm/atomic.h
+++ b/compel/arch/x86/src/lib/include/compel/asm/atomic.h
@@ -1,7 +1,7 @@
#ifndef __CR_ATOMIC_H__
#define __CR_ATOMIC_H__
-#include "asm/cmpxchg.h"
+#include "compel/asm/cmpxchg.h"
#define LOCK_PREFIX "\n\tlock; "
diff --git a/criu/arch/x86/include/asm/cmpxchg.h b/compel/arch/x86/src/lib/include/compel/asm/cmpxchg.h
similarity index 91%
rename from criu/arch/x86/include/asm/cmpxchg.h
rename to compel/arch/x86/src/lib/include/compel/asm/cmpxchg.h
index 600d0a7fff84..afed44055d0f 100644
--- a/criu/arch/x86/include/asm/cmpxchg.h
+++ b/compel/arch/x86/src/lib/include/compel/asm/cmpxchg.h
@@ -1,7 +1,7 @@
#ifndef __CR_CMPXCHG_H__
#define __CR_CMPXCHG_H__
-#include "asm/int.h"
+#include <stdint.h>
#define __X86_CASE_B 1
#define __X86_CASE_W 2
@@ -59,7 +59,7 @@
switch (size) { \
case __X86_CASE_B: \
{ \
- volatile u8 *__ptr = (volatile u8 *)(ptr); \
+ volatile uint8_t *__ptr = (volatile uint8_t *)(ptr); \
asm volatile(lock "cmpxchgb %2,%1" \
: "=a" (__ret), "+m" (*__ptr) \
: "q" (__new), "0" (__old) \
@@ -68,7 +68,7 @@
} \
case __X86_CASE_W: \
{ \
- volatile u16 *__ptr = (volatile u16 *)(ptr); \
+ volatile uint16_t *__ptr = (volatile uint16_t *)(ptr); \
asm volatile(lock "cmpxchgw %2,%1" \
: "=a" (__ret), "+m" (*__ptr) \
: "r" (__new), "0" (__old) \
@@ -77,7 +77,7 @@
} \
case __X86_CASE_L: \
{ \
- volatile u32 *__ptr = (volatile u32 *)(ptr); \
+ volatile uint32_t *__ptr = (volatile uint32_t *)(ptr); \
asm volatile(lock "cmpxchgl %2,%1" \
: "=a" (__ret), "+m" (*__ptr) \
: "r" (__new), "0" (__old) \
@@ -86,7 +86,7 @@
} \
case __X86_CASE_Q: \
{ \
- volatile u64 *__ptr = (volatile u64 *)(ptr); \
+ volatile uint64_t *__ptr = (volatile uint64_t *)(ptr); \
asm volatile(lock "cmpxchgq %2,%1" \
: "=a" (__ret), "+m" (*__ptr) \
: "r" (__new), "0" (__old) \
diff --git a/compel/arch/x86/src/lib/include/compel/asm/cpu.h b/compel/arch/x86/src/lib/include/compel/asm/cpu.h
new file mode 100644
index 000000000000..9e2c8b251b7f
--- /dev/null
+++ b/compel/arch/x86/src/lib/include/compel/asm/cpu.h
@@ -0,0 +1,177 @@
+#ifndef COMPEL_ASM_CPU_H__
+#define COMPEL_ASM_CPU_H__
+
+/*
+ * Adopted from linux kernel and enhanced from Intel/AMD manuals.
+ */
+
+#define NCAPINTS (12) /* N 32-bit words worth of info */
+#define NCAPINTS_BITS (NCAPINTS * 32)
+
+#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
+#define X86_FEATURE_VME (0*32+ 1) /* Virtual 8086 Mode Enhancements */
+#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
+#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extension */
+#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
+#define X86_FEATURE_MSR (0*32+ 5) /* Model Specific Registers RDMSR and WRMSR Instructions */
+#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extension */
+#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */
+#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
+#define X86_FEATURE_APIC (0*32+ 9) /* APIC On-Chip */
+#define X86_FEATURE_SEP (0*32+11) /* SYSENTER and SYSEXIT Instructions */
+#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
+#define X86_FEATURE_PGE (0*32+13) /* PTE Global Bit */
+#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
+#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
+#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
+#define X86_FEATURE_PSE36 (0*32+17) /* 36-Bit Page Size Extension */
+#define X86_FEATURE_PSN (0*32+18) /* Processor Serial Number */
+#define X86_FEATURE_DS (0*32+21) /* Debug Store */
+#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
+#define X86_FEATURE_ACPI (0*32+22) /* Thermal Monitor and Software Controlled Clock Facilities */
+#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
+#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
+#define X86_FEATURE_XMM (0*32+25) /* "sse" */
+#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
+#define X86_FEATURE_SS (0*32+27) /* Self Snoop */
+#define X86_FEATURE_HTT (0*32+28) /* Multi-Threading */
+#define X86_FEATURE_TM (0*32+29) /* Thermal Monitor */
+#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
+
+#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
+#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
+#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
+#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
+
+#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
+#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
+
+#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
+#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
+#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit DS Area */
+#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
+#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
+#define X86_FEATURE_VMX (4*32+ 5) /* Virtual Machine Extensions */
+#define X86_FEATURE_SMX (4*32+ 6) /* Safer Mode Extensions */
+#define X86_FEATURE_EST (4*32+ 7) /* Enhanced Intel SpeedStep technology */
+#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
+#define X86_FEATURE_CNXTID (4*32+10) /* L1 Context ID */
+#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
+#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
+#define X86_FEATURE_XTPR_UCTL (4*32+14) /* xTPR Update Control */
+#define X86_FEATURE_PDCM (4*32+15) /* Perfmon and Debug Capability */
+#define X86_FEATURE_PCID (4*32+17) /* Process-context identifiers */
+#define X86_FEATURE_DCA (4*32+18) /* Ability to prefetch data from a memory mapped device */
+#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
+#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
+#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
+#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
+#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
+#define X86_FEATURE_TSCDL (4*32+24) /* Local APIC timer supports one-shot operation using a TSC deadline value */
+#define X86_FEATURE_AES (4*32+25) /* AES instructions */
+#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
+#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
+#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
+
+#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
+#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
+#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
+#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
+#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
+#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
+
+#define X86_FEATURE_FSGSBASE (9*32+ 0) /* Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
+#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
+#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
+#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
+#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
+#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
+#define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 Foundation */
+#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
+#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
+#define X86_FEATURE_IPT (9*32+25) /* Intel Processor Trace */
+#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
+#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
+#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA (9*32+29) /* Intel SHA extensions */
+#define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 */
+#define X86_FEATURE_AVXVL (9*32+31) /* AVX-512 */
+
+#define X86_FEATURE_XSAVEOPT (10*32+0) /* XSAVEOPT */
+#define X86_FEATURE_XSAVEC (10*32+1) /* XSAVEC */
+#define X86_FEATURE_XGETBV1 (10*32+2) /* XGETBV with ECX = 1 */
+#define X86_FEATURE_XSAVES (10*32+3) /* XSAVES/XRSTORS */
+
+/*
+ * Node 11 is our own, kernel has not such entry.
+ */
+#define X86_FEATURE_PREFETCHWT1 (11*32+0) /* The PREFETCHWT1 instruction */
+
+static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ /* ecx is often an input as well as an output. */
+ asm volatile("cpuid"
+ : "=a" (*eax),
+ "=b" (*ebx),
+ "=c" (*ecx),
+ "=d" (*edx)
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
+}
+
+static inline void cpuid(unsigned int op,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ *eax = op;
+ *ecx = 0;
+ native_cpuid(eax, ebx, ecx, edx);
+}
+
+static inline void cpuid_count(unsigned int op, int count,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ *eax = op;
+ *ecx = count;
+ native_cpuid(eax, ebx, ecx, edx);
+}
+
+static inline unsigned int cpuid_eax(unsigned int op)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ cpuid(op, &eax, &ebx, &ecx, &edx);
+ return eax;
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ cpuid(op, &eax, &ebx, &ecx, &edx);
+ return ecx;
+}
+
+static inline unsigned int cpuid_edx(unsigned int op)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ cpuid(op, &eax, &ebx, &ecx, &edx);
+ return edx;
+}
+
+#endif /* COMPEL_ASM_CPU_H__ */
diff --git a/criu/arch/x86/include/asm/processor-flags.h b/compel/arch/x86/src/lib/include/compel/asm/processor-flags.h
similarity index 100%
rename from criu/arch/x86/include/asm/processor-flags.h
rename to compel/arch/x86/src/lib/include/compel/asm/processor-flags.h
diff --git a/criu/arch/aarch64/crtools.c b/criu/arch/aarch64/crtools.c
index 690c9d828987..4492f2b913b6 100644
--- a/criu/arch/aarch64/crtools.c
+++ b/criu/arch/aarch64/crtools.c
@@ -7,7 +7,7 @@
#include "asm/restorer.h"
#include "compiler.h"
#include "ptrace.h"
-#include "asm/processor-flags.h"
+#include "compel/asm/processor-flags.h"
#include "asm/dump.h"
#include "protobuf.h"
#include "images/core.pb-c.h"
diff --git a/criu/arch/arm/crtools.c b/criu/arch/arm/crtools.c
index 65e7f82e99f9..b944e6298ea6 100644
--- a/criu/arch/arm/crtools.c
+++ b/criu/arch/arm/crtools.c
@@ -6,7 +6,7 @@
#include "asm/dump.h"
#include "compiler.h"
#include "ptrace.h"
-#include "asm/processor-flags.h"
+#include "compel/asm/processor-flags.h"
#include "protobuf.h"
#include "images/core.pb-c.h"
#include "images/creds.pb-c.h"
diff --git a/criu/arch/x86/crtools.c b/criu/arch/x86/crtools.c
index 60b1e09cd7fa..01bbf7d0fb51 100644
--- a/criu/arch/x86/crtools.c
+++ b/criu/arch/x86/crtools.c
@@ -6,7 +6,7 @@
#include <sys/syscall.h>
#include <sys/auxv.h>
-#include "asm/processor-flags.h"
+#include "compel/asm/processor-flags.h"
#include "asm/parasite-syscall.h"
#include "asm/restorer.h"
#include "asm/types.h"
diff --git a/criu/arch/x86/include/asm/cpu.h b/criu/arch/x86/include/asm/cpu.h
index 6f49229d6396..24a1ccd7393e 100644
--- a/criu/arch/x86/include/asm/cpu.h
+++ b/criu/arch/x86/include/asm/cpu.h
@@ -1,182 +1,7 @@
#ifndef __CR_ASM_CPU_H__
#define __CR_ASM_CPU_H__
-#include "asm/types.h"
-
-/*
- * Adopted from linux kernel and enhanced from Intel/AMD manuals.
- */
-
-#define NCAPINTS (12) /* N 32-bit words worth of info */
-#define NCAPINTS_BITS (NCAPINTS * 32)
-
-#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
-#define X86_FEATURE_VME (0*32+ 1) /* Virtual 8086 Mode Enhancements */
-#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
-#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extension */
-#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR (0*32+ 5) /* Model Specific Registers RDMSR and WRMSR Instructions */
-#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extension */
-#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */
-#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
-#define X86_FEATURE_APIC (0*32+ 9) /* APIC On-Chip */
-#define X86_FEATURE_SEP (0*32+11) /* SYSENTER and SYSEXIT Instructions */
-#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
-#define X86_FEATURE_PGE (0*32+13) /* PTE Global Bit */
-#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
-#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
-#define X86_FEATURE_PSE36 (0*32+17) /* 36-Bit Page Size Extension */
-#define X86_FEATURE_PSN (0*32+18) /* Processor Serial Number */
-#define X86_FEATURE_DS (0*32+21) /* Debug Store */
-#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
-#define X86_FEATURE_ACPI (0*32+22) /* Thermal Monitor and Software Controlled Clock Facilities */
-#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
-#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
-#define X86_FEATURE_XMM (0*32+25) /* "sse" */
-#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
-#define X86_FEATURE_SS (0*32+27) /* Self Snoop */
-#define X86_FEATURE_HTT (0*32+28) /* Multi-Threading */
-#define X86_FEATURE_TM (0*32+29) /* Thermal Monitor */
-#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
-
-#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
-#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
-#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
-#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
-#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
-
-#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
-#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
-
-#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
-#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
-#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit DS Area */
-#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
-#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
-#define X86_FEATURE_VMX (4*32+ 5) /* Virtual Machine Extensions */
-#define X86_FEATURE_SMX (4*32+ 6) /* Safer Mode Extensions */
-#define X86_FEATURE_EST (4*32+ 7) /* Enhanced Intel SpeedStep technology */
-#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
-#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
-#define X86_FEATURE_CNXTID (4*32+10) /* L1 Context ID */
-#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
-#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
-#define X86_FEATURE_XTPR_UCTL (4*32+14) /* xTPR Update Control */
-#define X86_FEATURE_PDCM (4*32+15) /* Perfmon and Debug Capability */
-#define X86_FEATURE_PCID (4*32+17) /* Process-context identifiers */
-#define X86_FEATURE_DCA (4*32+18) /* Ability to prefetch data from a memory mapped device */
-#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
-#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
-#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
-#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
-#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
-#define X86_FEATURE_TSCDL (4*32+24) /* Local APIC timer supports one-shot operation using a TSC deadline value */
-#define X86_FEATURE_AES (4*32+25) /* AES instructions */
-#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
-#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
-#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
-#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
-#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
-
-#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
-#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
-#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
-#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
-#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
-#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
-#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
-
-#define X86_FEATURE_FSGSBASE (9*32+ 0) /* Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
-#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
-#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
-#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
-#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
-#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
-#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
-#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
-#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
-#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
-#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
-#define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 Foundation */
-#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
-#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
-#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
-#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
-#define X86_FEATURE_IPT (9*32+25) /* Intel Processor Trace */
-#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
-#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
-#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
-#define X86_FEATURE_SHA (9*32+29) /* Intel SHA extensions */
-#define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 */
-#define X86_FEATURE_AVXVL (9*32+31) /* AVX-512 */
-
-#define X86_FEATURE_XSAVEOPT (10*32+0) /* XSAVEOPT */
-#define X86_FEATURE_XSAVEC (10*32+1) /* XSAVEC */
-#define X86_FEATURE_XGETBV1 (10*32+2) /* XGETBV with ECX = 1 */
-#define X86_FEATURE_XSAVES (10*32+3) /* XSAVES/XRSTORS */
-
-/*
- * Node 11 is our own, kernel has not such entry.
- */
-#define X86_FEATURE_PREFETCHWT1 (11*32+0) /* The PREFETCHWT1 instruction */
-
-static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
- unsigned int *ecx, unsigned int *edx)
-{
- /* ecx is often an input as well as an output. */
- asm volatile("cpuid"
- : "=a" (*eax),
- "=b" (*ebx),
- "=c" (*ecx),
- "=d" (*edx)
- : "0" (*eax), "2" (*ecx)
- : "memory");
-}
-
-static inline void cpuid(unsigned int op,
- unsigned int *eax, unsigned int *ebx,
- unsigned int *ecx, unsigned int *edx)
-{
- *eax = op;
- *ecx = 0;
- native_cpuid(eax, ebx, ecx, edx);
-}
-
-static inline void cpuid_count(unsigned int op, int count,
- unsigned int *eax, unsigned int *ebx,
- unsigned int *ecx, unsigned int *edx)
-{
- *eax = op;
- *ecx = count;
- native_cpuid(eax, ebx, ecx, edx);
-}
-
-static inline unsigned int cpuid_eax(unsigned int op)
-{
- unsigned int eax, ebx, ecx, edx;
-
- cpuid(op, &eax, &ebx, &ecx, &edx);
- return eax;
-}
-
-static inline unsigned int cpuid_ecx(unsigned int op)
-{
- unsigned int eax, ebx, ecx, edx;
-
- cpuid(op, &eax, &ebx, &ecx, &edx);
- return ecx;
-}
-
-static inline unsigned int cpuid_edx(unsigned int op)
-{
- unsigned int eax, ebx, ecx, edx;
-
- cpuid(op, &eax, &ebx, &ecx, &edx);
- return edx;
-}
-
-#define X86_FEATURE_VERSION 1
+#include "compel/asm/cpu.h"
enum {
X86_VENDOR_INTEL = 0,
diff --git a/criu/cr-restore.c b/criu/cr-restore.c
index d682891aaf3c..ebc3026991ad 100644
--- a/criu/cr-restore.c
+++ b/criu/cr-restore.c
@@ -92,7 +92,7 @@
#include "images/siginfo.pb-c.h"
#include "asm/restore.h"
-#include "asm/atomic.h"
+#include "compel/asm/atomic.h"
#include "compel/asm/bitops.h"
#include "asm/parasite-syscall.h"
diff --git a/criu/files-reg.c b/criu/files-reg.c
index 7817fb4a7940..65f603bcd6be 100644
--- a/criu/files-reg.c
+++ b/criu/files-reg.c
@@ -23,7 +23,7 @@
#include "list.h"
#include "rst-malloc.h"
#include "fs-magic.h"
-#include "asm/atomic.h"
+#include "compel/asm/atomic.h"
#include "namespaces.h"
#include "proc_parse.h"
#include "pstree.h"
diff --git a/criu/include/cpu.h b/criu/include/cpu.h
index e94525a9e780..0f11e46513f1 100644
--- a/criu/include/cpu.h
+++ b/criu/include/cpu.h
@@ -1,7 +1,7 @@
#ifndef __CR_CPU_H__
#define __CR_CPU_H__
-#include "asm/cpu.h"
+#include "compel/asm/cpu.h"
extern bool cpu_has_feature(unsigned int feature);
extern int cpu_init(void);
diff --git a/criu/include/lock.h b/criu/include/lock.h
index f97fdd0534d9..3da1af7538ec 100644
--- a/criu/include/lock.h
+++ b/criu/include/lock.h
@@ -7,7 +7,7 @@
#include <limits.h>
#include <errno.h>
-#include "asm/atomic.h"
+#include "compel/asm/atomic.h"
#include "bug.h"
#ifdef CR_NOGLIBC
diff --git a/criu/parasite-syscall.c b/criu/parasite-syscall.c
index a001cfafb7f8..619506f19869 100644
--- a/criu/parasite-syscall.c
+++ b/criu/parasite-syscall.c
@@ -14,7 +14,7 @@
#include "imgset.h"
#include "ptrace.h"
-#include "asm/processor-flags.h"
+#include "compel/asm/processor-flags.h"
#include "parasite-syscall.h"
#include "parasite-blob.h"
#include "parasite.h"
diff --git a/criu/stats.c b/criu/stats.c
index a575e77d5511..d7298db6d060 100644
--- a/criu/stats.c
+++ b/criu/stats.c
@@ -1,7 +1,7 @@
#include <unistd.h>
#include <fcntl.h>
#include <sys/time.h>
-#include "asm/atomic.h"
+#include "compel/asm/atomic.h"
#include "rst-malloc.h"
#include "protobuf.h"
#include "stats.h"
--
2.7.4
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