[CRIU] [PATCH 4/9] nmk: build.mk -- Make process depend on Makefile itself

[Pavel Emelyanov]

> @@ -46,6 +47,16 @@ builtin-name	:= $(strip $(builtin-name))
>  ld_flags	:= $(strip $(LDFLAGS) $(ldflags-y))
>  
>  #
> +# $(obj) related rules.
> +$(eval $(call gen-rule-o-from-c-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-i-from-c-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-s-from-c-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-o-from-S-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-d-from-c-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-d-from-S-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))
> +$(eval $(call gen-rule-i-from-S-by-name,$(obj)/%,$(obj)/%,$(src-makefile)))

Please enlighten me. We're making o-from-c, i-from-c, s-from-c, blah-blah-blah
for a makeifle?

> +
> +#
>  # Prepare targets.
>  ifneq ($(lib-y),)
>          lib-target :=