[CRIU] [PATCH v2 0/6] ppc64: Transactional Memory support

[Laurent Dufour]

This series is providing the Transaction Memory (TM) support for
PowerPC.

TM operations have been introduced in POWER ISA 3.0 for Power 8
processors. Snippet from POWER ISA says:

"Transactional memory is a shared-memory synchronization construct
allowing an application to perform a sequence of storage accesses that
appear to occur atomically with respect to other threads."

The 4 first patches are fixing minor issues with the code, no
functional change, except error message's text.

The 5th patch is extracting part of code dealing with
the registers state to factorize this code with the TM support.

The latest patch is providing the TM state checkpoint / restart
through the new provided ptrace API dealing with the TM registers
state (see https://lkml.org/lkml/2016/7/27/656). This new ptrace API
is available in kernel starting release 4.8. 

v2: based on Dimitry Safonovi's comments.

Laurent Dufour (6):
  ppc64: review the comment style in proto file
  ppc64: Fix error message
  ppc64: rely on NVRREG define
  ppc64: introduces NVSXREG constant
  ppc64: Extract copy to protobuf functions
  ppc64: handle transactional memory state

 criu/arch/ppc64/crtools.c              | 573 ++++++++++++++++++++++++---------
 criu/arch/ppc64/include/asm/restorer.h |   8 +-
 criu/arch/ppc64/restorer.c             |  31 ++
 images/core-ppc64.proto                |  51 ++-
 4 files changed, 486 insertions(+), 177 deletions(-)

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2.7.4