[CRIU] [PATCH 03/15] cpuinfo: x86 -- Add needed bits and abbreviatures
Cyrill Gorcunov
gorcunov at openvz.org
Fri Sep 19 07:03:05 PDT 2014
These bits are needed to test CPU capability. In
particular we might need that in case of image
migration we're able to restore on target processors.
The bits definitions are taken from linux kernel.
They are not ABI strictly speaking but immutable
de-facto.
Signed-off-by: Cyrill Gorcunov <gorcunov at openvz.org>
---
arch/x86/cpu.c | 57 +++++++++++++++++++++++++++++++++++++---
arch/x86/include/asm/cpu.h | 65 +++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 118 insertions(+), 4 deletions(-)
diff --git a/arch/x86/cpu.c b/arch/x86/cpu.c
index e180d2306e9e..e800bf3b62f2 100644
--- a/arch/x86/cpu.c
+++ b/arch/x86/cpu.c
@@ -23,9 +23,60 @@
#define LOG_PREFIX "cpu: "
const char * const x86_cap_flags[NCAPINTS_BITS] = {
- [X86_FEATURE_FPU] = "fpu",
- [X86_FEATURE_FXSR] = "fxsr",
- [X86_FEATURE_XSAVE] = "xsave",
+ [X86_FEATURE_FPU] = "fpu",
+ [X86_FEATURE_CX8] = "cx8",
+ [X86_FEATURE_CMOV] = "cmov",
+ [X86_FEATURE_CLFLUSH] = "clflush",
+ [X86_FEATURE_MMX] = "mmx",
+ [X86_FEATURE_FXSR] = "fxsr",
+ [X86_FEATURE_XMM] = "sse",
+ [X86_FEATURE_XMM2] = "sse2",
+ [X86_FEATURE_SYSCALL] = "syscall",
+ [X86_FEATURE_MMXEXT] = "mmxext",
+ [X86_FEATURE_RDTSCP] = "rdtscp",
+ [X86_FEATURE_3DNOWEXT] = "3dnowext",
+ [X86_FEATURE_3DNOW] = "3dnow",
+ [X86_FEATURE_REP_GOOD] = "rep_good",
+ [X86_FEATURE_NOPL] = "nopl",
+ [X86_FEATURE_XMM3] = "pni",
+ [X86_FEATURE_PCLMULQDQ] = "pclmulqdq",
+ [X86_FEATURE_MWAIT] = "monitor",
+ [X86_FEATURE_TM2] = "tm2",
+ [X86_FEATURE_SSSE3] = "ssse3",
+ [X86_FEATURE_FMA] = "fma",
+ [X86_FEATURE_CX16] = "cx16",
+ [X86_FEATURE_XMM4_1] = "sse4_1",
+ [X86_FEATURE_XMM4_2] = "sse4_2",
+ [X86_FEATURE_MOVBE] = "movbe",
+ [X86_FEATURE_POPCNT] = "popcnt",
+ [X86_FEATURE_AES] = "aes",
+ [X86_FEATURE_XSAVE] = "xsave",
+ [X86_FEATURE_AVX] = "avx",
+ [X86_FEATURE_F16C] = "f16c",
+ [X86_FEATURE_RDRAND] = "rdrand",
+ [X86_FEATURE_ABM] = "abm",
+ [X86_FEATURE_SSE4A] = "sse4a",
+ [X86_FEATURE_MISALIGNSSE] = "misalignsse",
+ [X86_FEATURE_3DNOWPREFETCH] = "3dnowprefetch",
+ [X86_FEATURE_XOP] = "xop",
+ [X86_FEATURE_FMA4] = "fma4",
+ [X86_FEATURE_TBM] = "tbm",
+ [X86_FEATURE_XSAVEOPT] = "xsaveopt",
+ [X86_FEATURE_BMI1] = "bmi1",
+ [X86_FEATURE_HLE] = "hle",
+ [X86_FEATURE_AVX2] = "avx2",
+ [X86_FEATURE_BMI2] = "bmi2",
+ [X86_FEATURE_ERMS] = "erms",
+ [X86_FEATURE_INVPCID] = "invpcid",
+ [X86_FEATURE_RTM] = "rtm",
+ [X86_FEATURE_MPX] = "mpx",
+ [X86_FEATURE_AVX512F] = "avx512f",
+ [X86_FEATURE_RDSEED] = "rdseed",
+ [X86_FEATURE_ADX] = "adx",
+ [X86_FEATURE_CLFLUSHOPT] = "clflushopt",
+ [X86_FEATURE_AVX512PF] = "avx512pf",
+ [X86_FEATURE_AVX512ER] = "avx512er",
+ [X86_FEATURE_AVX512CD] = "avx512cd",
};
static DECLARE_BITMAP(cpu_features, NCAPINTS_BITS);
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 407610aa22e8..46fbd13a8e6c 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -7,12 +7,75 @@
* Adopted from linux kernel.
*/
-#define NCAPINTS (10) /* N 32-bit words worth of info */
+#define NCAPINTS (11) /* N 32-bit words worth of info */
#define NCAPINTS_BITS (NCAPINTS * 32)
#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
+#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
+#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
+#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
+#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
+#define X86_FEATURE_XMM (0*32+25) /* "sse" */
+#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
+
+#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
+#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
+#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
+#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
+
+#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
+#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
+
+#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
+#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
+#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
+#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
+
+#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
+#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
+#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
+#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
+#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
+#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
+#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
+#define X86_FEATURE_AES (4*32+25) /* AES instructions */
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
+#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
+#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
+
+#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
+#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
+#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
+#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
+#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
+#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
+
+#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
+#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
+#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
+#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
+#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
+#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
+#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
+#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
+#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
+#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
+
+#define X86_FEATURE_XSAVEOPT (10*32+0) /* XSAVEOPT */
+#define X86_FEATURE_XSAVEC (10*32+1) /* XSAVEC */
+#define X86_FEATURE_XGETBV1 (10*32+2) /* XGETBV with ECX = 1 */
+#define X86_FEATURE_XSAVES (10*32+3) /* XSAVES/XRSTORS */
extern const char * const x86_cap_flags[NCAPINTS_BITS];
--
1.9.3
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